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APL3208A/B/C
Li+ Charger Protection IC with Integrated P-MOSFET
Features
* * * * * * * * * * *
Input Over-Voltage Protection Current-Limit Protection Battery Over-Voltage Protection High Immunity of False Triggering High Accuracy Protection Threshold A Built-In P-MOSFET Available with 3 Versions of Charging Current: 450mA, 550mA, 650mA Thermal Shutdown Protection Available in TDFN2x2-8 and TSOT-23-6A Packages "Lithium-Safe" Criteria Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APL3208A/B/C provides complete Li+ charger protection against Input over-voltage, battery over-voltage, and the charge current limit. When the input OVP or the battery OVP is over the threshold, the IC removes the power from the charging system by turning off an internal switch. When the current via the internal switch surpasses the current limit threshold, the current will be clamped in a constant level to provide a constant current for battery charging usage. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3208A/B/C integrates a P-MOSFET with the body diode reverse protection to replace the external power bipolar transistor and Schottky diode for charger function of the Infineon ULC2 mobile phones. When the CHG_DET voltage drops below VBAT+20mV, the internal power select circuit will reverse the body diode' terminal to pres vent a reverse current flowing from the battery back to the CHG_DET pin. The APL3208A/B/C provides complete Li+ charger protections and save the external MOSFET and Schottky diode for the Infineon ULC2 mobile phones. The above
8 OUT 7 OUT 6 CHG_DET 5 CHG_SW
Applications
*
Cell Phones for Infineon
Pin Configuration
ACIN 1 ACIN 2 GND 3 VBAT 4
features and small package make the APL3208A/B/C an ideal part for cell phones applications.
EP
Simplified Application Circuit
5V Adapter or USB VCHG_DET ACIN CHG_DET APL3208A/B/C CHG_SW OUT GND VBAT Li+ Battery CHG_SW
TDFN2x2-8 (Top View)
EP
= Exposed Pad (Connected to the ground plane for better heat dissipation)
R
OUT 1 CHG_DET 2 CHG_SW 3
TSOT-23-6A (Top View)
6 ACIN 5 GND 4 VBAT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Nov., 2009 1 www.anpec.com.tw
APL3208A/B/C
Ordering and Marking Information
APL3208A APL3208B APL3208C Package Code QB : TDFN2x2-8 CT : TSOT-23-6A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device X - Date Code
Assembly Material Handling Code Temperature Range Package Code L08A X L08B X L08C X L8AX L8BX L8CX
APL3208A
QB:
APL3208B
QB:
X - Date Code
APL3208C APL3208A APL3208B APL3208C
QB: CT: CT: CT:
X - Date Code X - Date Code X - Date Code X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings (Note 1)
Symbol VACIN VCHG_DET VCHG_SW VBAT VOUT IOUT TJ TSTG TSDR Parameter ACIN Input Voltage (ACIN to GND) CHG_DET to GND Voltage CHG_SW to GND Voltage VBAT to GND Voltage OUT to GND Voltage OUT Output Current Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds Rating -0.3 ~ 30 -0.3 ~ 7 -0.3 ~ VCHG_DET -0.3 ~ 7 -0.3 ~ 7 1.5 150 -65 ~ 150 260 Unit V V V V V A
o
C C
o o
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA Parameter Junction-to-Ambient Resistance in Free Air
(Note 2)
Typical Value TDFN2x2-8 TSOT-23-6A 80 235
Unit
o
C/W
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Nov., 2009 2 www.anpec.com.tw
APL3208A/B/C
Recommended Operating Conditions (Note 3)
Symbol VACIN TA TJ ACIN Input Voltage Ambient Temperature Junction Temperature Parameter Range 4.5 ~ 5.5 -40 ~ 85 -40 ~ 125 Unit V
o o
C
C
Note 3: Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions APL3208A/B/C Min. Typ. Max. Unit
ACIN INPUT CURRENT AND POWER-ON-RESET (POR) IACIN VACIN ACIN Supply Current ACIN POR Threshold ACIN POR Hysteresis TB(ACIN) ACIN Power-On Blanking Time IOUT=0A, ICHG_DET=0A VACIN rising 2.4 200 250 250 8 350 2.8 300 A V mV ms
INTERNAL SWITCH ON RESISTANCE CHG_DET Discharge On Resistance INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP Input OVP Threshold Input OVP Hysteresis Input OVP Propagation Delay TON(OVP) Input OVP Recovery Time VACIN rising 6 200 6.17 300 8 6.35 400 1 V mV s ms 500
CURRENT-LIMIT PROTECTION APL3208A, TA=25C ILIM Current Limit Threshold APL3208B, TA=25C APL3208C, TA=25C BATTERY OVER-VOLTAGE PROTECTION VBOVP Battery OVP Threshold Battery OVP Hysteresis IVBAT TB(BOVP) VBAT Pin Leakage Current Battery OVP Blanking Time VBAT = 4.4V VBAT rising 4.32 220 4.35 270 176 4.38 320 20 V mV nA s 400 500 600 450 550 650 500 600 700 mA
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS) VCHG_DET-VBAT Lockout Threshold OUT Input Current CHG_SW Leakage Current OUT Leakage Current VCHG_DET from low to high, P-MOSFET is controlled by CHG_SW VCHG_DET from high to low, P-MOSFET is off VCHG_DET=0V, VOUT=4.2V, CHG_SW =GND VACIN=VCHG_DET= VOUT=5V, VCHG_SW=0V VACIN=VCHG_DET= VCHG_SW =5V, VOUT=0V 120 20 7.5 1 13 1 A A A mV
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Nov., 2009
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APL3208A/B/C
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APL3208A/B/C Min. Typ. Max.
Unit
INTERNAL P-MOSFET (CHG_DET, OUT AND CHG_SW PINS) (CONT.) P-MOSFET Input Capacitance CHG_SW Input Resistance OVER-TEMPERATURE PROTECTION (OTP) TOTP Over-Temperature Threshold Over-Temperature Hysteresis TJ rising 160 40 C C 200 15 pF
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APL3208A/B/C
Operating Waveforms
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Normal Power On
OVP at Power On
VACIN 1 VOUT 1
VACIN
VCHG_DET 2 VCHG_DET 2,3 VOUT
IOUT 4 3
CACIN =1F, COUT =1F, VCHG_SW CHG_DET =V CH1: VACIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VCHG_DET, 2V/Div, DC CH4: I OUT, 0.2A/Div, DC TIME: 2ms/Div
CACIN =1F, COUT =1F CH1: VACIN, 10V/Div, DC CH2: VCHG_DET, 1V/Div, DC CH3: VOUT, 2V/Div, DC TIME: 2ms/Div
Input Over-Voltage Protection
Recovery from Input OVP
VACIN
VACIN
1
1
VCHG_DET
VCHG_DET 2
2
VOUT 3
VACIN to 12V, VCHG_SW No Load =5V = 0V, CACIN =1F, COUT =1F CH1: VACIN, 5V/Div, AC CH2: VCHG_DET, 2V/Div, DC TIME:20s/Div
VACIN 12V to 5V, VCHG_SW CHG_DET = =V CACIN =1F, COUT =1F CH1: VACIN, 5V/Div, AC CH2: VCHG_DET, 2V/Div, DC CH3: VOUT, 2V/Div, DC TIME: 2ms/Div
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APL3208A/B/C
Operating Waveforms (Cont.)
The test condition is VACIN=5V, VBAT=3.8V, TA= 25oC unless otherwise specified.
Battery Over-Voltage Protection
Battery Over-Voltage Protection
VBAT
VBAT 1
1 VCHG_DET
VCHG_DET
2
2
VBAT = 3.6V to 4.4V to 3.6V CACIN =1F, COUT =1F CH1: VBAT, 2V/Div, DC CH2: VCHG_DET, 2V/Div, DC TIME: 50ms/Div
VBAT = 3.6V to 4.4V CACIN=1F, COUT =1F CH1: VBAT, 2V/Div, DC CH2: VCHG_DET, 2V/Div, DC TIME: 200s/Div
Pin Description
PIN NO. TDFN2x2-8 TSOT-23-6A 1, 2 3 4 5 6 7, 8 Exposed Pad 6 5 4 3 2 1 ACIN GND VBAT CHG_SW CHG_DET OUT EP Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1F (minimum) ceramic capacitor. Ground Terminal. Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor. Internal P-MOSFET Gate Input. Output Pin. This pin provides supply voltage to the Infineon ULC2 input. Bypass to GND with a 1F (minimum) ceramic capacitor. Output Pins. These pins provide supply source current in series with a resistor to battery. Exposed Thermal Pad. Must be electrically connected to the GND pin. NAME FUNCTION
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Nov., 2009
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APL3208A/B/C
Block Diagram
ACIN
CHG_DET
POR OUT Charge Pump
ACIN OVP 0.5V
Gate Driver and Control Logic
VBAT OVP
1V
CHG_SW
GND Thermal Shutdown VBAT
Typical Application Circuit
5V Adapter or USB
1, 2
CACIN 1F
ACIN
CHG_DET
6
C1 1F
5 7, 8
CHG_DET R2 2.2k 20~100k R1 C2 33nF Infineon ULC2 CHG_SW
APL3208A/B/C CHG_SW OUT
3
GND
VBAT
4
VBAT RBAT 200k Li+ Battery
(Optional)
Designation CACIN C1
Description 1F, 50V, X7R, 0805 Murata GRM21BR71H105K 1F, 10V, X7R, 0805 Murata GRM21BR71A105K
Murata website: www.murata.com
Figure 1. Infineon ULC2 Application Circuit
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APL3208A/B/C
Typical Application Circuit (Cont.)
1, 2 CACIN 1F
ACIN
CHG_DET
6 COUT 1F 5 7, 8 4 RBAT 200k Li+ Battery
CHG_DET
APL3208 CHG_SW OUT 3 GND VBAT
PMIC CHG_SW
VBAT
(Optional)
Designation CACIN COUT
Description 1F, 50V, X7R, 0805 Murata GRM21BR71H105K 1F, 10V, X7R, 0805 Murata GRM21BR71A105K
Murata website: www.murata.com
Figure 2. General Application Circuit
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APL3208A/B/C
Function Description
ACIN Power-On-Reset (POR) The APL3208A/B/C has a built-in power-on-reset circuit to keep the output shutting off until internal circuitry is operating properly. The POR circuit has hysteresis and a de-glitch feature so that it will typically ignore undershoot transients on the input. When the input voltage exceeds the POR threshold and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. ACIN Over-Voltage Protection (OVP) The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP threshold, the internal FET will be turned off within 1ms to protect the connected system on OUT pin. When the input voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery time. The input OVP circuit has a 200mV hysteresis and a recovery time of TON(OVP) to provide noise immunity against transient conditions. Battery Over-Voltage Protection The APL3208A/B/C monitors the VBAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the VBAT pin voltage exceeds the battery OVP threshold for a blanking time of TB , the internal power FET is turned off. When the VBAT (BOVP) voltage returns below the battery OVP threshold minus the hysteresis, the FET is turned on again. The APL3208A/ B/C has a built-in counter. When the total count of battery OVP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. Current-Limit Protection The APL3208A/B/C provides a current-limit protection function. When the current via the internal switch surpasses the current limit threshold, the current will be clamped to a constant level to provide external battery charging current. Over-Temperature Protection When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and allows the device to cool down. When the device' juncs tion temperature cools by 40 oC, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over temperature conditions. For normal operation, the junction temperature cannot exceed TJ=+125oC. Internal P-MOSFET The APL3208A/B/C integrates a P-channel MOSFET with the body diode reverse protection to replace the external power bipolar transistor and Schottky diode for the Infineon ULC2 mobile. The body diode reverse protection prevents a reverse current flowing from the battery back to the CHG_DET pin. During power-on, when CHG_DET voltage rises above the VBAT voltage by more than 120mV, the body diode of the P-channel MOSFET is forward biased from OUT to CHG_DET, and P-MOSFET is controlled by the external CHG_SW voltage. When the CHG_DET voltage drops below VBAT+20mV, the body diode of the P-channel MOSFET is forward biased from CHG_DET to OUT and P-channel MOSFET is turned off. When any of input OVP, battery OVP, is detected,the internal P-channel MOSFET is also turned off.
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APL3208A/B/C
Function Description (Cont.)
VOVP VPOR VACIN VCHG_DET -VBAT = 120mV VCHG_DET -VBAT = 120mV
VCHG_DET
VOUT CHG_SW is pulled low
P-MOS Gate Control
Turn Off Internal P-MOSFET TB(ACIN)
Controlled by CHG_SW
Turn Off Internal P-MOSFET
Controlled by CHG_SW
ACIN OVP
TON(OVP)
Figure 3. OVP Timing Diagram
VBAT
VBOVP VCHG_DET -VOUT = 120mV
VBOVP
VCHG_DET
Count 13 times Turn Off Internal P-OSFET
P-MOS Gate Controlled Control by CHG_SW
Turn Off Internal P-MOSFET
Controlled by CHG_SW
Controlled by CHG_SW
Turn Off Internal P-MOSFET Total count 16 times, IC is latched off
TB(BOVP)
TB(BOVP)
TB(BOVP)
Figure 4. Battery OVP Timing Diagram
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APL3208A/B/C
Application Information
RBAT Selection Connect the VBAT pin to the positive terminal of battery through a resistor RBAT for battery OVP function. The RBAT limits the current flowing from VBAT to battery in case of VBAT pin is shortened to ACIN pin under a failure mode. The recommended value of RBAT is 200k. In the worse case of an IC failure, the current flowing from the VBAT pin to the battery is: (30V-3V)/ 200k =135A where the 30V is the maximum ACIN voltage and the 3V is the minimum battery voltage. The current is so small and can be absorbed by the charger system. Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A 50V, X7R, dielectric ceramic capacitor with a value between 1F and 4.7F placed close to the ACIN pin is recommended. The output capacitor of CHG_DET is for CHG_DET voltage decoupling. And also can be as the input capacitor of the charging circuit. At least, a 1F, 10V, X7R capacitor is recommended. Layout Consideration In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the function of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current traces like input trace and output trace must be wide and short.
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APL3208A/B/C
Package Information
TDFN2x2-8
D
A
E
D2 A1 A3
Pin 1 Corner
e S Y M B O L A A1 A3 b D D2 E E2 e L 0.30 0.18 1.90 1.00 1.90 0.60 0.50 BSC 0.45 0.012 TDFN2x2-8 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.30 2.10 1.60 2.10 1.00 0.007 0.075 0.039 0.075 0.024 0.020 BSC 0.018 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 0.083 0.063 0.083 0.039 INCHES MAX. 0.031 0.002
Note : 1. Follow from JEDEC MO-229 WCCD-3.
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L
E2
b
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APL3208A/B/C
Package Information
TSOT-23-6A
D e
SEE VIEW A
E1 b e1
E
c
A2
A
0.25 GAUGE PLANE SEATING PLANE L VIEW A TSOT-23-6A INCHES MIN. 0.028 0.000 0.028 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.60 8 0.012 0 0.024 8 MAX. 0.039 0.004 0.035 0.020 0.008 0.122 0.118 0.071 MAX. 1.00 0.10 0.90 0.50 0.20 3.10 3.00 1.80
S Y M B O L A A1 A2 b c D E E1 e e1 L 0
MILLIMETERS MIN. 0.70 0.01 0.70 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0
Note : Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Nov., 2009
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APL3208A/B/C
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 178.0O .00 2
H 50 MIN. P1 4.0O .10 0 H 50 MIN. P1 4.0O .10 0
H A
T1
T1 8.4+2.00 -0.00 P2 2.0O .05 0 T1 8.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.5 MIN. d 1.5 MIN. D1 1.0 MIN.
D 20.2 MIN. T 0.6+0.00 -0.4 D 20.2 MIN. T 0.6+0.00 -0.40
W 8.0O .20 0 A0 3.35 MIN W 8.0O .30 0 A0 3.20O .20 0
E1 1.75O .10 0 B0 3.35 MIN E1 1.75O .10 0 B0 3.10O .20 0
W
F 3.50O .05 0 K0 1.30O .20 0 F 3.5O .05 0 K0 1.50O .20 0 (mm)
TDFN2x2-8
P0 4.0O .10 0
Application
A 178.0O .00 2
TSOT-23-6A
P0 4.0O .10 0
Devices Per Unit
Package Type TDFN2x2-8 TSOT-23-6A Unit Tape & Reel Tape & Reel Quantity 3000 3000
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APL3208A/B/C
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
TSOT-23-6A
USER DIRECTION OF FEED
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
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APL3208A/B/C
Classification Profile
Classification Reflow Profiles
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
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APL3208A/B/C
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C
3
Volume mm 350-2000 260 C 250 C 245 C
3
Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV VMMU200V 10ms, 1trU 100mA
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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